This disclosure relates to semiconductor circuits, and more particularly, to a circuit for generating a refresh period signal (i.e., refresh period signal generation circuit) and a semiconductor integrated circuit using the same.
Semiconductor integrated circuits, e.g., volatile memories such as dynamic random access memories (DRAMs) are often times essentially equipped with refresh operations for retaining data stored in their memory cells.
These DRAMs are generally designed to periodically conduct the refresh operations even when in standby states for which there is no event of reading or writing operations.
In operation of DRAMs, refresh period signals are normally used for defining periods of the refresh operations.
FIG. 1 illustrates a general organization of a refresh period signal generation circuit.
As shown in FIG. 1, the general refresh period signal generation circuit 1 includes an oscillator 10, a frequency divider 20, and a pulse generation unit 30.
The oscillator 10 is shown generating an oscillation signal OSC in response to a refresh duration signal SREF that functions to determine a refresh period.
The frequency divider 20 is shown generating a plurality of frequency signals operating in 1 μs, 2 μs, 4 μs, 8 μs and 16 μs by dividing the oscillation signal OSC.
The pulse generation unit 30 is shown outputting a refresh period signal SREFP from one of the frequency signals (1 μs, 2 μs, 4 μs, 8 μs and 16 μs) which is selected in accordance with a fuse option signal FSEL.
FIG. 2 shows a waveform of an output signal generated from the period signal generation circuit of FIG. 1.
The refresh duration signal SREF is inactivated when there is an input of a refresh escape command SREX. The refresh escape command SREX is generated regardless of an operating status of the refresh period signal generation circuit. In other words, without relevance to output signals of the oscillator 10, the frequency divider 20 and the pulse generation unit 30, the refresh escape signal SREX is independently generated to inactivate the refresh duration signal SREF.
It is first assumed that the pulse generation unit 30 makes the refresh period signal SREFP from one of the plural frequency signals (1 μs, 2 μs, 4 μs, 8 μs and 16 μs), e.g., the 8 μs frequency signal.
As shown in FIG. 2, when the refresh duration signal SREF is inactivated by the refresh escape command SREX at the time when the oscillation signal OSC is generated, i.e., when the refresh duration signal SREF is inactivated by the refresh escape command SREX while the 8 μs frequency signal is generated from the oscillation signal OSC, the 8 μs frequency signal may be abnormally generated without a sufficient timing margin.
Owing to such an insufficient timing margin of the 8 μs frequency signal, the refresh period signal SREFP responding thereto is also generated in a form of glitch without a sufficient timing margin.
As the refresh operation to memory cells is carried out by selecting a row address corresponding to the memory cells in accordance with a pulse of the refresh period signal SREFP, the abnormal glitch of the refresh period signal SREFP causes the row address not to be selected.
Therefore, cell data are prone to being damaged or compromised because the memory cells corresponding to the row address that has not been yet selected are abnormally conditioned in an incomplete state of the refresh operation.
Such a timing distortion between the refresh escape command SREX and the oscillation signal OSC occurs irregularly, resulting in the glitch of the refresh period signal SREFP. For that reason, it is practically difficult to predict when the refresh period signal SREFP is generated with such an insufficient and abnormal pulse in the glitch. And it is difficult to make the glitch effect reemerged even by a test process because the refresh escape command SREX is independently applied thereto regardless of an operating status of the refresh period signal generation circuit. Simply adjusting a delay time of a signal involved therein does not bring about a adequate solution against the trouble of timing distortion between the refresh escape command SREX and the oscillation signal OSC. As a result, there would be an inadvertent defect in the memory apparatus such as DRAM.